Return-to-zero (RZ) digital-to-analog converter (DAC) for image cancellation

ABSTRACT

Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example device for digital-to-analog conversion generally includes: a digital-to-analog converter (DAC) having an input coupled to an input node of the device; a first return-to-zero (RZ) DAC having an input coupled to an input node of the device; and a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the first RZ DAC is coupled to a second input of the combiner.

TECHNICAL FIELD

Certain aspects of the present disclosure generally relate to electroniccircuits and, more particularly, to circuitry for digital-to-analogconversion.

BACKGROUND

A wireless communication network may include a number of base stationsthat can support communication for a number of mobile stations. A mobilestation (MS) may communicate with a base station (BS) via a downlink andan uplink. The downlink (or forward link) refers to the communicationlink from the base station to the mobile station, and the uplink (orreverse link) refers to the communication link from the mobile stationto the base station. A base station may transmit data and controlinformation on the downlink to a mobile station and/or may receive dataand control information on the uplink from the mobile station. The basestation and/or mobile station may include one or more digital-to-analogconverters (DACs) for converting digital signals to analog signals.

SUMMARY

The systems, methods, and devices of the disclosure each have severalaspects, no single one of which is solely responsible for its desirableattributes. Without limiting the scope of this disclosure as expressedby the claims that follow, some features are discussed briefly below.After considering this discussion, and particularly after reading thesection entitled “Detailed Description,” one will understand how thefeatures of this disclosure provide the advantages described herein.

Certain aspects of the present disclosure generally relate to circuitryand techniques for digital-to-analog conversion.

Certain aspects are directed to a device for digital-to-analogconversion. The device generally includes a digital-to-analog converter(DAC) having an input coupled to an input node of the device, a firstreturn-to-zero (RZ) DAC having an input coupled to an input node of thedevice, and a combiner, wherein an output of the DAC is coupled to afirst input of the combiner, and wherein an output of the first RZ DACis coupled to a second input of the combiner.

Certain aspects are directed to a method for digital-to-analogconversion. The method generally includes generating, via a DAC, a firstanalog signal by performing digital-to-analog conversion based on adigital input signal, generating, via a first RZ DAC, a second analogsignal by performing digital-to-analog conversion based on the digitalinput signal, and combining the first analog signal and the secondanalog signal to generate a combined analog signal.

Certain aspects are directed to an apparatus for digital-to-analogconversion. The apparatus generally includes a DAC configured togenerate a first analog signal by performing digital-to-analogconversion based on a digital input signal, a first RZ DAC configured togenerate a second analog signal by performing digital-to-analogconversion based on the digital input signal, and a combiner configuredto combine the first analog signal and the second analog signal togenerate a combined analog signal.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above-recited features of the presentdisclosure can be understood in detail, a more particular description,briefly summarized above, may be had by reference to aspects, some ofwhich are illustrated in the appended drawings. It is to be noted,however, that the appended drawings illustrate only certain typicalaspects of this disclosure and are therefore not to be consideredlimiting of its scope, for the description may admit to other equallyeffective aspects.

FIG. 1 is a diagram of an example wireless communications network, inaccordance with certain aspects of the present disclosure.

FIG. 2 is a block diagram of an example access point (AP) and exampleuser terminals, in accordance with certain aspects of the presentdisclosure.

FIG. 3 is a block diagram of an example transceiver front end, inaccordance with certain aspects of the present disclosure.

FIG. 4 is a graph illustrating an analog output of a zero-order holddigital-to-analog converter (DAC).

FIG. 5 illustrates a DAC system including a zero-order hold DAC and oneor more return-to-zero (RZ) DACs, in accordance with certain aspects ofthe present disclosure.

FIG. 6A illustrates a DAC system including a zero-order hold DAC and twoRZ DACs receiving sampling clocks having different frequencies, inaccordance with certain aspects of the present disclosure.

FIG. 6B illustrates graphs showing analog output signals for the DACsystem of FIG. 6A, in accordance with certain aspects of the presentdisclosure.

FIG. 7A illustrates a DAC system including a zero-order hold DAC andthree RZ DACs receiving sampling clocks having the same frequency, butdifferent phases, in accordance with certain aspects of the presentdisclosure.

FIG. 7B illustrates graphs showing analog output signals for the DACsystem of FIG. 7A, in accordance with certain aspects of the presentdisclosure.

FIG. 8A illustrates a DAC system including a zero-order hold DAC andthree RZ DACs receiving sampling clocks with different duty cycles,different phases, and the same frequency, in accordance with certainaspects of the present disclosure.

FIG. 8B illustrates graphs showing analog output signals for the DACsystem of FIG. 8A, in accordance with certain aspects of the presentdisclosure.

FIG. 9A illustrates a DAC system including a zero-order hold DAC andthree RZ DACs receiving sampling clocks with the same duty cycle and thesame frequency, but different phases, in accordance with certain aspectsof the present disclosure.

FIG. 9B illustrates graphs showing analog output signals for the DACsystem of FIG. 9A, in accordance with certain aspects of the presentdisclosure.

FIG. 10A illustrates a DAC system including a zero-order hold DAC andtwo RZ DACs receiving three-phase sampling clocks with different dutycycles, in accordance with certain aspects of the present disclosure.

FIG. 10B illustrates graphs showing analog output signals for the DACsystem of FIG. 10A, in accordance with certain aspects of the presentdisclosure.

FIG. 11 is a flow diagram illustrating example operations fordigital-to-analog conversion, in accordance with certain aspects of thepresent disclosure.

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures. It is contemplated that elements disclosed in one aspectmay be beneficially utilized on other aspects without specificrecitation.

DETAILED DESCRIPTION

Certain aspects of the present disclosure generally relate to electroniccircuits and, more particularly, to circuitry for digital-to-analogconversion. In some aspects, an analog signal generated by adigital-to-analog converter (DAC) (e.g., a zero-order hold DAC) may becombined with one or more output signals generated by one or morereturn-to-zero (RZ) DACs. The RZ DACs serve to cancel (or at leastreduce) image signals at the output of a DAC system including thezero-order hold DAC and the one or more RZ DACs. As a result of samplingtaking place in the zero-order hold DAC, the analog signal generated bythe zero-order hold DAC may be different than an ideal analog signalvalue representing a digital input to the DAC system. This difference(e.g., error) may result in image signals being generated at the outputof the DAC system. As described, the analog signal generated by an RZDAC may be combined with the analog signal generated by the zero-orderhold DAC, such that there is a smaller difference between the combinedanalog output signal and the ideal analog signal value, as compared tothe difference between the zero-order hold DAC analog output signal andthe ideal analog signal value. Therefore, the image signals at theoutput of the DAC system may be reduced, as described in more detailherein.

Various aspects of the disclosure are described more fully hereinafterwith reference to the accompanying drawings. This disclosure may,however, be embodied in many different forms and should not be construedas limited to any specific structure or function presented throughoutthis disclosure. Rather, these aspects are provided so that thisdisclosure will be thorough and complete, and will fully convey thescope of the disclosure to those skilled in the art. Based on theteachings herein, one skilled in the art should appreciate that thescope of the disclosure is intended to cover any aspect of thedisclosure disclosed herein, whether implemented independently of orcombined with any other aspect of the disclosure. For example, anapparatus may be implemented or a method may be practiced using anynumber of the aspects set forth herein. In addition, the scope of thedisclosure is intended to cover such an apparatus or method which ispracticed using other structure, functionality, or structure andfunctionality in addition to or other than the various aspects of thedisclosure set forth herein. It should be understood that any aspect ofthe disclosure disclosed herein may be embodied by one or more elementsof a claim.

The word “exemplary” is used herein to mean “serving as an example,instance, or illustration.” Any aspect described herein as “exemplary”is not necessarily to be construed as preferred or advantageous overother aspects.

As used herein, the term “connected with” in the various tenses of theverb “connect” may mean that element A is directly connected to elementB or that other elements may be connected between elements A and B(i.e., that element A is indirectly connected with element B). In thecase of electrical components, the term “connected with” may also beused herein to mean that a wire, trace, or other electrically conductivematerial is used to electrically connect elements A and B (and anycomponents electrically connected therebetween).

An Example Wireless System

FIG. 1 illustrates a wireless communications system 100 with accesspoints 110 and user terminals 120, in which aspects of the presentdisclosure may be practiced. For simplicity, only one access point 110is shown in FIG. 1 . An access point (AP) is generally a fixed stationthat communicates with the user terminals and may also be referred to asa base station (BS), an evolved Node B (eNB), or some other terminology.A user terminal (UT) may be fixed or mobile and may also be referred toas a mobile station (MS), an access terminal, user equipment (UE), astation (STA), a client, a wireless device, or some other terminology. Auser terminal may be a wireless device, such as a cellular phone, apersonal digital assistant (PDA), a handheld device, a wireless modem, alaptop computer, a tablet, a personal computer, etc.

Access point 110 may communicate with one or more user terminals 120 atany given moment on the downlink and uplink. The downlink (i.e., forwardlink) is the communication link from the access point to the userterminals, and the uplink (i.e., reverse link) is the communication linkfrom the user terminals to the access point. A user terminal may alsocommunicate peer-to-peer with another user terminal. A system controller130 couples to and provides coordination and control for the accesspoints.

System 100 employs multiple transmit and multiple receive antennas fordata transmission on the downlink and uplink. Access point 110 may beequipped with a number N_(ap) of antennas to achieve transmit diversityfor downlink transmissions and/or receive diversity for uplinktransmissions. A set N_(u) of selected user terminals 120 may receivedownlink transmissions and transmit uplink transmissions. Each selecteduser terminal transmits user-specific data to and/or receivesuser-specific data from the access point. In general, each selected userterminal may be equipped with one or multiple antennas (i.e., N_(ut)≥1).The N_(u) selected user terminals can have the same or different numberof antennas.

Wireless system 100 may be a time division duplex (TDD) system or afrequency division duplex (FDD) system. For a TDD system, the downlinkand uplink share the same frequency band. For an FDD system, thedownlink and uplink use different frequency bands. System 100 may alsoutilize a single carrier or multiple carriers for transmission. Eachuser terminal 120 may be equipped with a single antenna (e.g., to keepcosts down) or multiple antennas (e.g., where the additional cost can besupported). In certain aspects of the present disclosure, the accesspoint 110 and/or user terminal 120 may include a digital-to-analogconverter (DAC) system implemented using one or more return-to-zero (RZ)DACs for image cancellation, as described in more detail herein.

FIG. 2 shows a block diagram of access point 110 and two user terminals120 m and 120 x in wireless system 100. Access point 110 is equippedwith N_(ap) antennas 224 a through 224 ap. User terminal 120 m isequipped with N_(ut,m) antennas 252 ma through 252 mu, and user terminal120 x is equipped with N_(ut,x) antennas 252 xa through 252 xu. Accesspoint 110 is a transmitting entity for the downlink and a receivingentity for the uplink. Each user terminal 120 is a transmitting entityfor the uplink and a receiving entity for the downlink. As used herein,a “transmitting entity” is an independently operated apparatus or devicecapable of transmitting data via a frequency channel, and a “receivingentity” is an independently operated apparatus or device capable ofreceiving data via a frequency channel. In the following description,the subscript “dn” denotes the downlink, the subscript “up” denotes theuplink, N_(up) user terminals are selected for simultaneous transmissionon the uplink, N_(dn) user terminals are selected for simultaneoustransmission on the downlink, N_(up) may or may not be equal to N_(dn),and N_(up) and N_(dn) may be static values or can change for eachscheduling interval. Beam-steering or some other spatial processingtechnique may be used at the access point and user terminal.

On the uplink, at each user terminal 120 selected for uplinktransmission, a TX data processor 288 receives traffic data from a datasource 286 and control data from a controller 280. TX data processor 288processes (e.g., encodes, interleaves, and modulates) the traffic data{d_(up)} for the user terminal based on the coding and modulationschemes associated with the rate selected for the user terminal andprovides a data symbol stream {s_(up)} for one of the N_(ut,m) antennas.A transceiver front end (TX/RX) 254 (also known as a radio frequencyfront end (RFFE)) receives and processes (e.g., converts to analog,amplifies, filters, and frequency upconverts) a respective symbol streamto generate an uplink signal. The transceiver front end 254 may alsoroute the uplink signal to one of the N_(ut,m) antennas for transmitdiversity via a radio-frequency (RF) switch, for example. The controller280 may control the routing within the transceiver front end 254. Memory282 may store data and program codes for the user terminal 120 and mayinterface with the controller 280.

A number N_(up) of user terminals 120 may be scheduled for simultaneoustransmission on the uplink. Each of these user terminals transmits itsset of processed symbol streams on the uplink to the access point.

At access point 110, N_(ap) antennas 224 a through 224 ap receive theuplink signals from all N_(up) user terminals transmitting on theuplink. For receive diversity, a transceiver front end 222 may selectsignals received from one of the antennas 224 for processing. Thesignals received from multiple antennas 224 may be combined for enhancedreceive diversity. The access point's transceiver front end 222 alsoperforms processing complementary to that performed by the userterminal's transceiver front end 254 and provides a recovered uplinkdata symbol stream. The recovered uplink data symbol stream is anestimate of a data symbol stream {s_(up)} transmitted by a userterminal. An RX data processor 242 processes (e.g., demodulates,deinterleaves, and decodes) the recovered uplink data symbol stream inaccordance with the rate used for that stream to obtain decoded data.The decoded data for each user terminal may be provided to a data sink244 for storage and/or a controller 230 for further processing. Incertain aspects, the transceiver front end (TX/RX) 222 of access point110 and/or transceiver front end 254 of user terminal 120 may include aDAC system implemented using one or more return-to-zero (RZ) DACs forimage cancellation, as described in more detail herein.

On the downlink, at access point 110, a TX data processor 210 receivestraffic data from a data source 208 for N_(dn) user terminals scheduledfor downlink transmission, control data from a controller 230 andpossibly other data from a scheduler 234. The various types of data maybe sent on different transport channels. TX data processor 210 processes(e.g., encodes, interleaves, and modulates) the traffic data for eachuser terminal based on the rate selected for that user terminal. TX dataprocessor 210 may provide a downlink data symbol streams for one of moreof the N_(dn) user terminals to be transmitted from one of the N_(ap)antennas. The transceiver front end 222 receives and processes (e.g.,converts to analog, amplifies, filters, and frequency upconverts) thesymbol stream to generate a downlink signal. The transceiver front end222 may also route the downlink signal to one or more of the N_(ap)antennas 224 for transmit diversity via an RF switch, for example. Thecontroller 230 may control the routing within the transceiver front end222. Memory 232 may store data and program codes for the access point110 and may interface with the controller 230.

At each user terminal 120, N_(ut,m) antennas 252 receive the downlinksignals from access point 110. For receive diversity at the userterminal 120, the transceiver front end 254 may select signals receivedfrom one of the antennas 252 for processing. The signals received frommultiple antennas 252 may be combined for enhanced receive diversity.The user terminal's transceiver front end 254 also performs processingcomplementary to that performed by the access point's transceiver frontend 222 and provides a recovered downlink data symbol stream. An RX dataprocessor 270 processes (e.g., demodulates, deinterleaves, and decodes)the recovered downlink data symbol stream to obtain decoded data for theuser terminal.

FIG. 3 is a block diagram of an example transceiver front end 300, suchas transceiver front ends 222, 254 in FIG. 2 , in which aspects of thepresent disclosure may be practiced. The transceiver front end 300includes a transmit (TX) path 302 (also known as a transmit chain) fortransmitting signals via one or more antennas and a receive (RX) path304 (also known as a receive chain) for receiving signals via theantennas. When the TX path 302 and the RX path 304 share an antenna 303,the paths may be connected with the antenna via an interface 306, whichmay include any of various suitable RF devices, such as a duplexer, aswitch, a diplexer, and the like.

Receiving in-phase (I) or quadrature (Q) baseband analog signals from adigital-to-analog converter (DAC) 308, the TX path 302 may include abaseband filter (BBF) 310, a mixer 312, a driver amplifier (DA) 314, anda power amplifier (PA) 316. The DAC 308 may be implemented using one ormore return-to-zero (RZ) DACs for image cancellation, as described inmore detail herein. The BBF 310, the mixer 312, and the DA 314 may beincluded in a radio frequency integrated circuit (RFIC), while the PA316 may be external to the RFIC. The BBF 310 filters the basebandsignals received from the DAC 308, and the mixer 312 mixes the filteredbaseband signals with a transmit local oscillator (LO) signal to convertthe baseband signal of interest to a different frequency (e.g.,upconvert from baseband to RF). This frequency conversion processproduces the sum and difference frequencies of the LO frequency and thefrequency of the signal of interest. The sum and difference frequenciesare referred to as the beat frequencies. The beat frequencies aretypically in the RF range, such that the signals output by the mixer 312are typically RF signals, which may be amplified by the DA 314 and/or bythe PA 316 before transmission by the antenna 303.

The RX path 304 includes a low noise amplifier (LNA) 322, a mixer 324,and a baseband filter (BBF) 326. The LNA 322, the mixer 324, and the BBF326 may be included in a radio frequency integrated circuit (RFIC),which may or may not be the same RFIC that includes the TX pathcomponents. RF signals received via the antenna 303 may be amplified bythe LNA 322, and the mixer 324 mixes the amplified RF signals with areceive local oscillator (LO) signal to convert the RF signal ofinterest to a different baseband frequency (i.e., downconvert). Thebaseband signals output by the mixer 324 may be filtered by the BBF 326before being converted by an analog-to-digital converter (ADC) 328 todigital I or Q signals for digital signal processing.

Tuning the LO to different frequencies typically entails using avariable-frequency oscillator, which may involve compromises betweenstability and tunability. Some systems may employ frequency synthesizerswith a voltage-controlled oscillator (VCO) to generate a stable, tunableLO with a particular tuning range. Thus, the transmit LO frequency maybe produced by a TX frequency synthesizer 318, which may be buffered oramplified by amplifier 320 before being mixed with the baseband signalsin the mixer 312. Similarly, the receive LO frequency may be produced byan RX frequency synthesizer 330, which may be buffered or amplified byamplifier 332 before being mixed with the RF signals in the mixer 324.

While FIGS. 1-3 provide a wireless communication system as an exampleapplication in which certain aspects of the present disclosure may beimplemented to facilitate understanding, certain aspects describedherein may be used for digital-to-analog conversion in any of variousother suitable systems.

Example Digital-to-Analog Converter (DAC)

The digital-to-analog converter (DAC) (e.g., DAC 308) used in wirelessapplications creates image signals around multiple harmonics of thesampling frequency (fs) of the DAC. Wireless communication standards mayset tight limits on power emissions, and thus, it may be desirable toattenuate image signals in an effort to reduce emitted power atout-of-band frequencies.

One way to reduce/attenuate the power of the image signals is toincrease the DAC effective sampling rate (e.g., by using interpolatingDACs). However, this approach may result in increased DAC powerconsumption. In wideband applications, a wideband baseband signal andtechnology limited sampling frequency (fs) results in a low deltabetween the frequency of the image and signal, making it challenging tofilter out the image signal. Therefore, what is needed are apparatus andtechniques for removing, or at least reducing the power of, imagesignals of a DAC in a power efficient manner.

Certain aspects of the present disclosure use one or more return-to-zero(RZ) DACs in parallel with a zero-order hold DAC to cancel image signalsassociated with the zero-order hold DAC. An RZ DAC generally refers to aDAC having an analog output representing a digital input signal duringonly a portion of a cycle of a clock provided to the RZ DAC. Forexample, an RZ DAC receiving a 50% duty cycle (DC) clock may provide ananalog output for half the clock cycle and a zero volt output during theother half of the clock cycle. Similarly, an RZ DAC receiving a 25% dutycycle clock may provide an analog output for 25% of the clock cycle anda zero volt output during the other 75% of the clock cycle. In contrast,a zero-order hold DAC typically samples a digital input at the beginningof a clock cycle and generates an analog output held until the nextclock cycle.

FIG. 4 is a graph 400 illustrating an analog output 452 of a DAC (e.g.,zero-order hold DAC) over time. The ideal waveform 450 represents aperfect representation of a digital input to the zero-order hold DAC. Asshown, the analog output 452 of the main DAC does not track the idealwaveform, resulting in image signals as described. For example, at times402, 404, 406, 408, 410 (e.g., representing the beginning of respectiveclock cycles at the sampling frequency (fs)), the zero-order hold DACsamples a digital input and provides an associated analog output. Thus,at times 402, 404, 406, 408, 410, the analog output may be about thesame as the ideal waveform. However, between times 402, 404, 406, 408,410, the analog output is held at a constant voltage and is differentthan the ideal waveform, causing the image signals. In some aspects ofthe present disclosure, a DAC system is implemented with a zero-orderhold DAC and one or more RZ DACs to generate an analog output that moreclosely tracks the ideal waveform, in effect reducing the power of theimage signals.

FIG. 5 illustrates a digital-to-analog conversion system 500 including azero-order hold DAC and one or more RZ DACs (e.g., auxiliary DACs), inaccordance with certain aspects of the present disclosure. For example,the digital-to-analog conversion system 500 may include a zero-orderhold DAC 502 and RZ DACs 504-1 to 504-n, n being an integer greaterthan 1. The RZ DACs 504-1 to 504-n (labeled “RZ DAC_(aux_1)” to “RZDAC_(aux_n)”) are collectively referred to herein as “RZ DACs 504.”While FIG. 5 illustrates three RZ DACs to facilitate understanding, theaspects described herein may be implemented with any number of RZ DACs.As shown, the output of the zero-order hold DAC 502 and the RZ DACs 504are combined using a combiner 510 to generate an analog output of thedigital-to-analog conversion system 500.

As shown, the DAC 502 may receive a clock signal, the frequency of theclock signal setting the sampling frequency (fs) of the DAC 502. Theclock signal is labeled “fs” in FIG. 5 . Similarly, the RZ DACs 504receive respective clock signals labeled “Fs_aux_1” to “Fs_aux_n” inFIG. 5 , each clock signal setting a sampling frequency of a respectiveone of the RZ DACs 504.

A digital filter circuit 506 (H₁(z)) may be coupled to the input of theDAC 502, and digital filter circuits 508-1 to 508-n (labeled“H_(aux_1)(z)” to “H_(aux_n)(z)”) may be coupled to respective inputs ofthe RZ DACs 504. Digital filter circuits 508-1 to 508-n are collectivelyreferred to as “digital filter circuits 508”, n being an integer greaterthan 1. For example, there may be three digital filter circuits 508-1,508-2, and 508-3 in some aspects. Each of the digital filter circuits506, 508 may receive a digital signal at a digital input 520, andprovide a filtered version of the digital signal to a respective one ofthe DACs 502, 504. The digital filter circuits 506, 508 may beimplemented as finite impulse response (FIR) filters (e.g.,interpolators).

FIG. 6A illustrates a digital-to-analog conversion system 600 includingRZ DACs 504-1 and 504-2, in accordance with certain aspects of thepresent disclosure. As shown, the DAC 502 receives a clock signal havinga frequency fs, the RZ DAC 504-1 receives a clock signal (having afrequency fs) that is the inverse of the clock signal provided to theDAC 502, and the RZ DAC 504-2 receives a clock signal having a frequencyof 2fs.

FIG. 6B illustrates a graph 602 showing the output of the combiner 510of FIG. 6A, a graph 604 showing the output of the RZ DAC 504-1 of FIG.6A, and a graph 606 showing the output of the RZ DAC 504-2 of FIG. 6A.For each RZ DAC (e.g., RZ DAC 504-1), a digital filter (e.g., digitalfilter circuit 508-1) generates a filtered digital input such that theRZ DAC (e.g., in combination with another RZ DAC) generates an analogoutput representing the difference between the ideal waveform 450 andthe analog output 452 of the DAC 502. For example, the RZ DAC 504-2generates an analog output 650 representing the difference between theanalog output 452 and the ideal waveform 450. The RZ DAC 504-2 alsogenerates analog output 652, that when combined with the analog output654 generated by RZ DAC 504-1, represents the difference between theanalog output 452 and the ideal waveform 450.

The RZ DAC 504-1 samples and provides an analog output at a frequency offs, and the RZ DAC 504-1 samples and provides an analog output at afrequency of 2fs, as shown by graphs 604, 606, respectively. As shown bygraph 602, the analog outputs of the RZ DACs 504-1 and 504-2 fill in thegap between the analog output 452 and the ideal waveform 450, in effectcanceling (or at least reducing) the image signals associated withdigital-to-analog conversion. The RZ DAC 504-1 reduces the image signalsnear fs and 3fs, and the RZ DAC 504-2 reduces the image signals near2fs.

FIG. 7A illustrates a digital-to-analog conversion system 700 includingRZ DACs 504-1 and 504-2, as well as RZ DAC 504-3, in accordance withcertain aspects of the present disclosure. As shown, the DAC 502receives a clock signal having a frequency fs and 50% duty cycle, the RZDAC 504-1 receives a clock signal having a frequency fs (which is fswith a 180° phase shift relative to the clock signal of DAC 502) that isthe inverse of the clock signal provided to the DAC 502, and the RZ DAC504-2 receives a clock signal having a frequency of fs with a 90° phaseshift (e.g., relative to the clock signal of DAC 502) and 25% dutycycle, and RZ DAC 504-3 receives a clock signal having a frequency of fswith a 270° phase shift (e.g., relative to the clock signal of DAC 502)and a 25% duty cycle.

FIG. 7B illustrates a graph 702 showing the output of the combiner 510of FIG. 7A, a graph 704 showing the output of the RZ DAC 504-1 of FIG.7A, a graph 706 showing the output of the RZ DAC 504-2 of FIG. 7A, and agraph 708 showing the output of the RZ DAC 504-3 of FIG. 7A. The RZ DAC504-1 samples and provides an analog output at a frequency of fs asshown by graph 704. The RZ DAC 504-1 samples and provides an analogoutput based on a clock signal having a frequency of fs with a 25% dutycycle and 90° phase shift (e.g., relative to the clock signal of DAC502) as shown by graph 706. The RZ DAC 504-2 samples and provides ananalog output based on a clock signal having a frequency of fs with a25% duty cycle and 270° phase shift (e.g., relative to the clock signalof DAC 502) as shown by graph 708.

As shown by graph 702, the analog outputs of the RZ DACs 504-1, 504-2,and 504-3 fill in the gap between the analog output 452 generated by DAC502 and the ideal waveform 450, in effect canceling (or at leastreducing) the image signals associated with digital-to-analogconversion. The RZ DAC 504-1 reduces the image signals near fs and 3fs,and the RZ DACs 504-2 and 504-3 reduce the image signals near 2fs.

FIG. 8A illustrates a digital-to-analog conversion system 800 includingRZ DACs 504-1, 504-2, and 504-3, in accordance with certain aspects ofthe present disclosure. As shown, the DAC 502 receives a clock signalhaving a frequency fs and 50% duty cycle. The RZ DAC 504-1 receives aclock signal having a frequency fs, which is the inverse of the clocksignal provided to the DAC 502 (or could also be considered as fs with a180° phase shift). The RZ DAC 504-2 receives a clock signal having afrequency of fs with a 90° phase shift (e.g., relative to the clocksignal of DAC 502) and 75% duty cycle. The RZ DAC 504-3 receives a clocksignal having a frequency of fs with a 270° phase shift (e.g., relativeto the clock signal of DAC 502) and a 25% duty cycle.

FIG. 8B illustrates a graph 802 showing the output of the combiner 510of FIG. 8A, a graph 804 showing the output of the RZ DAC 504-1 of FIG.8A, a graph 806 showing the output of the RZ DAC 504-2 of FIG. 8A, and agraph 808 showing the output of the RZ DAC 504-3 of FIG. 8A. The RZ DAC504-1 samples and provides an analog output based on a clock signalhaving a frequency of fs as shown by graph 804. The RZ DAC 504-1 samplesand provides an analog output based on a clock signal having a frequencyof fs with a 75% duty cycle and 90° phase shift, as shown by graph 806.The RZ DAC 504-2 samples and provides an analog output based on a clocksignal having a frequency of fs with a 25% duty cycle and 270° phaseshift as shown by graph 808. As shown by graph 802, the analog outputsof the RZ DACs 504-1, 504-2, and 504-3 fill in the gap between theanalog output 452 generated by DAC 502 and the ideal waveform 450, ineffect canceling (or at least reducing) the image signals associatedwith digital-to-analog conversion.

Implementing the RZ DACs with different duty cycles (e.g., 25%, 50%, and75%) reduces the amplitude of the analog output generated by the RZDACs. In other words, regardless of the digital input, the outputs ofthe RZ DACs are combined to fill the gap between the analog output 452and the ideal waveform 450. Thus, the analog output 850 of the RZ DAC504-1 may have a relatively lower amplitude as compared to the analogoutput of RZ DAC 504-1 in other implementations (e.g., analog output 654shown in FIG. 6B).

FIG. 9A illustrates a digital-to-analog conversion system 900 includingRZ DACs 504-1, 504-2, and 504-3, in accordance with certain aspects ofthe present disclosure. As shown, the DAC 502 receives a clock signalhaving a frequency fs, the RZ DAC 504-1 receives a clock signal having afrequency fs with a 180° phase shift and a 25% duty cycle, the RZ DAC504-2 receives a clock signal having a frequency of fs with a 90° phaseshift and a 25% duty cycle, and RZ DAC 504-3 receives a clock signalhaving a frequency of fs with a 270° phase shift and a 25% duty cycle.

FIG. 9B illustrates a graph 902 showing the output of the combiner 510of FIG. 9A, a graph 904 showing the output of the RZ DAC 504-1 of FIG.9A, a graph 906 showing the output of the RZ DAC 504-2 of FIG. 9A, and agraph 908 showing the output of the RZ DAC 504-3 of FIG. 9A. The RZ DAC504-1 samples and provides an analog output based on a clock signalhaving a frequency of fs with a 25% duty cycle and 180° phase shift asshown by graph 904. The RZ DAC 504-2 samples and provides an analogoutput based on a clock signal having a frequency of fs with a 25% dutycycle and 90° phase shift as shown by graph 906. The RZ DAC 504-3samples and provides an analog output based on a clock signal having afrequency of fs with a 25% duty cycle and 270° phase shift as shown bygraph 908. As shown by graph 802, the analog outputs of the RZ DACs504-1, 504-2, and 504-3 fill in the gap between the analog output 452generated by DAC 502 and the ideal waveform 450, in effect canceling (orat least reducing) the image signals associated with digital-to-analogconversion.

Implementing the RZ DACs with the same duty cycles (e.g., 25%) anddifferent phase shifts results in the RZ DACs providing non-overlappinganalog outputs. As a result, the same current source may be used toprovide power to the RZ DACs. In other words, since only one of the RZDACs is generating an analog output at any particular time, the samecurrent source may be used for the RZ DACs, reducing the areaconsumption of the DAC hardware.

FIG. 10A illustrates a digital-to-analog conversion system 1000including RZ DACs 504-1 and 504-2, in accordance with certain aspects ofthe present disclosure. As shown, the DAC 502 receives a clock signalhaving a frequency fs, the RZ DAC 504-1 receives a clock signal having afrequency of fs with a 120° phase shift and 66% duty cycle, and RZ DAC504-2 receives a clock signal having a frequency of fs with a 240° phaseshift and a 33% duty cycle.

FIG. 10B illustrates a graph 1002 showing the output of the combiner 510of FIG. 10A, a graph 1004 showing the output of the RZ DAC 504-1 of FIG.10A, and a graph 1006 showing the output of the RZ DAC 504-2 of FIG.10A. The RZ DAC 504-1 samples and provides an analog output based on aclock signal having a frequency of fs with a 66% duty cycle and 120°phase shift as shown by graph 1004, and the RZ DAC 504-2 samples andprovides an analog output based on a clock signal having a frequency offs with a 33% duty cycle and 240° phase shift as shown by graph 1006.

As shown by graph 1002, the analog outputs of the RZ DACs 504-1 and504-2 fill in the gap between the analog output 452 generated by DAC 502and the ideal waveform 450, in effect canceling (or at least reducing)the image signals associated with digital-to-analog conversion, near fsand 2fs. The implementation shown in FIGS. 10A and 10B allows forreduction of image signals with less hardware (e.g., only two RZ DACsinstead of three), but involves generating a 3-phase clock and using 33%and 66% duty cycles.

Using the RZ DACs provides a more precise DAC image cancellationarchitecture as compared to conventional implementations. Some aspectsallow for FIR coefficient design reuse from another digitalinterpolator. In other words, one or more coefficients used to implementthe digital filter circuit 506 may also be used for one or more ofdigital filter circuits 508. Using the RZ DACs for image cancellationprovides an analog output with less band-edge droop than conventionalimplementations. That is, the output signal of conventional DACs mayhave a voltage droop at the sampling frequency, which is reduced whenusing the RZ DAC image cancellation technique described herein. The RZDAC image cancellation technique also provides flexibility in decidinghow many image signals to cancel and can be combined with other imagecancellation techniques, such as DAC interleaving techniques.

FIG. 11 is a flow diagram illustrating example operations 1100 fordigital-to-analog conversion, in accordance with certain aspects of thepresent disclosure. The operations 1100 may be performed, for example,by a DAC system such as the digital-to-analog conversion system 500 ofFIG. 5 , the digital-to-analog conversion system 600 of FIG. 6A, thedigital-to-analog conversion system 700 of FIG. 7A, thedigital-to-analog conversion system 800 of FIG. 8A, thedigital-to-analog conversion system 900 of FIG. 9A, or thedigital-to-analog conversion system 1000 of FIG. 10A.

The operations 1100 begin, at block 1102, with the DAC systemgenerating, via a DAC (e.g., zero-order hold DAC 502), a first analogsignal by performing digital-to-analog conversion based on a digitalinput signal (e.g., at digital input 520). At block 1104, the DAC systemgenerates, via a first RZ DAC (e.g., RZ DAC 504-1), a second analogsignal by performing digital-to-analog conversion based on the digitalinput signal. For example, the second analog signal may have a magnitudethat is equal to a difference between the first analog signal and avalue representing the digital input signal. At block 1106, the DACsystem combines (e.g., via combiner 510) the first analog signal and thesecond analog signal to generate a combined analog signal.

In some aspects, the DAC system also generates, via a second RZ DAC(e.g., RZ DAC 504-2), a third analog signal based on the digital inputsignal. The combining at block 1106 may include combining the firstanalog signal, the second analog signal, and the third analog signal.

In some aspects, the first analog signal is generated based on a firstsampling clock (e.g., a clock signal having a frequency fs as shown inFIG. 6A). The second analog signal (e.g., generated by RZ DAC 504-1shown in FIG. 6A) may be generated based on a second sampling clock(e.g., having a frequency fs), the second sampling clock having the samefrequency as the first sampling clock. The second sampling clock may bephase-shifted from the first sampling clock by 180°. The third analogsignal (e.g., generated by RZ DAC 504-2 shown in FIG. 6A) may begenerated based on a third sampling clock, the third sampling clockhaving a frequency that is twice a frequency of the first samplingclock.

In some aspects, the DAC system generates, via a third RZ DAC (e.g.,504-3), a fourth analog signal based on the digital input signal. Thecombining at block 1106 includes combining the first analog signal, thesecond analog signal, the third analog signal, and the fourth analogsignal.

In some aspects, the first analog signal is generated based on a firstsampling clock, and the second analog signal (e.g., generated by RZ DAC504-1 shown in FIG. 7A) is generated based on a second sampling clock,the second sampling clock having the same frequency and having a phaseshift of 180° as compared to the first sampling clock. Moreover, thethird analog signal (e.g., generated by RZ DAC 504-2 shown in FIG. 7A)is generated based on a third sampling clock having a 25% duty cycle,the third sampling clock having the same frequency and having a phaseshift of 90° as compared to the first sampling clock. The fourth analogsignal (e.g., generated by RZ DAC 504-3 shown in FIG. 7A) may begenerated based on a fourth sampling clock having a 25% duty cycle, thefourth sampling clock having the same frequency and having a phase shiftof 270° as compared to the first sampling clock.

In some aspects, the first analog signal (e.g., generated by DAC 502shown in FIG. 8A) is generated based on a first sampling clock, and thesecond analog signal (e.g., generated by RZ DAC 504-1 shown in FIG. 8A)is generated based on a second sampling clock, the second sampling clockhaving the same frequency and having a phase shift of 180° as comparedto the first sampling clock. Moreover, the third analog signal may begenerated based on a third sampling clock having a 75% duty cycle, thethird sampling clock having the same frequency and having a phase shiftof 90° as compared to the first sampling clock, and the fourth analogsignal may be generated based on a fourth sampling clock having a 25%duty cycle, the fourth sampling clock having the same frequency andhaving a phase shift of 270° as compared to the first sampling clock.

In some aspects, the first analog signal (e.g., generated by RZ DAC504-2 shown in FIG. 9A) is generated based on a first sampling clock,and the second analog signal (e.g., generated by RZ DAC 504-1 shown inFIG. 9A) is generated based on a second sampling clock having a 25% dutycycle, the second sampling clock having the same frequency and having aphase shift of 180° as compared to the first sampling clock. Moreover,the third analog signal (e.g., generated by RZ DAC 504-2 shown in FIG.9A) may be generated based on a third sampling clock having a 25% dutycycle, the third sampling clock having the same frequency and having aphase shift of 90° as compared to the first sampling clock, and thefourth analog signal (e.g., generated by RZ DAC 504-3 shown in FIG. 9A)may be generated based on a fourth sampling clock having a 25% dutycycle, the fourth sampling clock having the same frequency and having aphase shift of 270° as compared to the first sampling clock.

In some aspects, the first analog signal (e.g., generated by DAC 502shown in FIG. 10A) is generated based on a first sampling clock, and thesecond analog signal (e.g., generated by RZ DAC 504-1 shown in FIG. 10A)is generated based on a second sampling clock having a 66% duty cycle,the second sampling clock having the same frequency and having a phaseshift of 120° as compared to the first sampling clock. Moreover, thethird analog signal (e.g., generated by RZ DAC 504-2 shown in FIG. 10A)may be generated based on a third sampling clock having a 33% dutycycle, the third sampling clock having the same frequency and having aphase shift of 240° as compared to the first sampling clock.

In some aspects, the DAC system generates, via a first filter circuit(e.g., digital filter circuit 506), a first filtered version of thedigital input signal, wherein the first analog signal is generated basedon the first filtered version of the digital input signal. The DACsystem also generates, via a second filter circuit (e.g., digital filtercircuit 508-1), a second filtered version of the digital input signal,wherein the second analog signal is generated based on the secondfiltered version of the digital input signal.

EXAMPLE ASPECTS

In addition to the various aspects described above, specificcombinations of aspects are within the scope of the disclosure, some ofwhich are detailed below:

Aspect 1. A device for digital-to-analog conversion, comprising: adigital-to-analog converter (DAC) having an input coupled to an inputnode of the device; a first return-to-zero (RZ) DAC having an inputcoupled to the input node of the device; and a combiner, wherein anoutput of the DAC is coupled to a first input of the combiner, andwherein an output of the first RZ DAC is coupled to a second input ofthe combiner.

Aspect 2. The device of claim 1, further comprising a second RZ DAChaving an input coupled to the input node of the device, wherein anoutput of the second RZ DAC is coupled to a third input of the combiner.

Aspect 3. The device of claim 2, wherein: the DAC is configured toperform digital-to-analog conversion of an input signal at the inputnode based on a first sampling clock; the first RZ DAC is configured toperform digital-to-analog conversion of the input signal based on asecond sampling clock, the second sampling clock having the samefrequency as the first sampling clock; and the second RZ DAC isconfigured to perform digital-to-analog conversion of the input signalbased on a third sampling clock, the third sampling clock having afrequency that is twice the frequency of the first sampling clock.

Aspect 4. The device of claim 3, wherein the second sampling clock isphase shifted from the first sampling clock by 180°.

Aspect 5. The device of claim 2, further comprising a third RZ DAChaving an input coupled to the input node of the device, wherein anoutput of the third RZ DAC is coupled to a fourth input of the combiner.

Aspect 6. The device of claim 5, wherein: the DAC is configured toperform digital-to-analog conversion of an input signal at the inputnode based on a first sampling clock; the first RZ DAC is configured toperform digital-to-analog conversion of the input signal based on asecond sampling clock, the second sampling clock having the samefrequency and having a phase shift of 180° as compared to the firstsampling clock; the second RZ DAC is configured to performdigital-to-analog conversion of the input signal based on a thirdsampling clock having a 25% duty cycle, the third sampling clock havingthe same frequency and having a phase shift of 90° as compared to thefirst sampling clock; and the third RZ DAC is configured to performdigital-to-analog conversion of the input signal based on a fourthsampling clock having a 25% duty cycle, the fourth sampling clock havingthe same frequency and having a phase shift of 270° as compared to thefirst sampling clock.

Aspect 7. The device of claim 5, wherein: the DAC is configured toperform digital-to-analog conversion of an input signal at the inputnode based on a first sampling clock; the first RZ DAC is configured toperform digital-to-analog conversion of the input signal based on asecond sampling clock, the second sampling clock having the samefrequency and having a phase shift of 180° as compared to the firstsampling clock; the second RZ DAC is configured to performdigital-to-analog conversion of the input signal based on a thirdsampling clock having a 75% duty cycle, the third sampling clock havingthe same frequency and having a phase shift of 90° as compared to thefirst sampling clock; and the third RZ DAC is configured to performdigital-to-analog conversion of the input signal based on a fourthsampling clock having a 25% duty cycle, the fourth sampling clock havingthe same frequency and having a phase shift of 270° as compared to thefirst sampling clock.

Aspect 8. The device of claim 5, wherein: the DAC is configured toperform digital-to-analog conversion of an input signal at the inputnode based on a first sampling clock; the first RZ DAC is configured toperform digital-to-analog conversion of the input signal based on asecond sampling clock having a 25% duty cycle, the second sampling clockhaving the same frequency and having a phase shift of 180° as comparedto the first sampling clock; the second RZ DAC is configured to performdigital-to-analog conversion of the input signal based on a thirdsampling clock having a 25% duty cycle, the third sampling clock havingthe same frequency and having a phase shift of 90° as compared to thefirst sampling clock; and the third RZ DAC is configured to performdigital-to-analog conversion of the input signal based on a fourthsampling clock having a 25% duty cycle, the fourth sampling clock havingthe same frequency and having a phase shift of 270° as compared to thefirst sampling clock.

Aspect 9. The device of claim 2, wherein: the DAC is configured toperform digital-to-analog conversion of an input signal at the inputnode based on a first sampling clock; the first RZ DAC is configured toperform digital-to-analog conversion of the input signal based on asecond sampling clock having a 66% duty cycle, the second sampling clockhaving the same frequency and having a phase shift of 120° as comparedto the first sampling clock; and the second RZ DAC is configured toperform digital-to-analog conversion of the input signal based on athird sampling clock having a 33% duty cycle, the third sampling clockhaving the same frequency and having a phase shift of 240° as comparedto the first sampling clock.

Aspect 10. The device of claim 1, further comprising: a first filtercircuit coupled between the input node of the device and the input ofthe DAC; and a second filter circuit coupled between the input node ofthe device and the input of the DAC, wherein the second filter circuithas a different transfer function than the first filter circuit.

Aspect 11. The device of claim 1, wherein: the DAC is configured togenerate a first analog signal based on a digital input signal; and thefirst RZ DAC is configured to generate a second analog signal, thesecond analog signal having a magnitude that is equal to a differencebetween the first analog signal and a value representing the digitalinput signal.

Aspect 12. The device of claim 1, wherein the first DAC comprises azero-order hold DAC.

Aspect 13. A method for digital-to-analog conversion, comprising:generating, via a digital-to-analog converter (DAC), a first analogsignal by performing digital-to-analog conversion based on a digitalinput signal; generating, via a first return-to-zero (RZ) DAC, a secondanalog signal by performing digital-to-analog conversion based on thedigital input signal; and combining the first analog signal and thesecond analog signal to generate a combined analog signal.

Aspect 14. The method of claim 13, further comprising generating, via asecond RZ DAC, a third analog signal based on the digital input signal,wherein the combining includes combining the first analog signal, thesecond analog signal, and the third analog signal.

Aspect 15. The method of claim 14, wherein: the first analog signal isgenerated based on a first sampling clock; the second analog signal isgenerated based on a second sampling clock, the second sampling clockhaving the same frequency as the first sampling clock; and the thirdanalog signal is generated based on a third sampling clock, the thirdsampling clock having a frequency that is twice the frequency of thefirst sampling clock.

Aspect 16. The method of claim 15, wherein the second sampling clock isphase shifted from the first sampling clock by 180°.

Aspect 17. The method of claim 14, further comprising: generating, via athird RZ DAC, a fourth analog signal based on the digital input signal,wherein the combining includes combining the first analog signal, thesecond analog signal, the third analog signal, and the fourth analogsignal.

Aspect 18. The method of claim 17, wherein: the first analog signal isgenerated based on a first sampling clock; the second analog signal isgenerated based on a second sampling clock, the second sampling clockhaving the same frequency and having a phase shift of 180° as comparedto the first sampling clock; the third analog signal is generated basedon a third sampling clock having a 25% duty cycle, the third samplingclock having the same frequency and having a phase shift of 90° ascompared to the first sampling clock; and the fourth analog signal isgenerated based on a fourth sampling clock having a 25% duty cycle, thefourth sampling clock having the same frequency and having a phase shiftof 270° as compared to the first sampling clock.

Aspect 19. The method of claim 17, wherein: the first analog signal isgenerated based on a first sampling clock; the second analog signal isgenerated based on a second sampling clock, the second sampling clockhaving the same frequency and having a phase shift of 180° as comparedto the first sampling clock; the third analog signal is generated basedon a third sampling clock having a 75% duty cycle, the third samplingclock having the same frequency and having a phase shift of 90° ascompared to the first sampling clock; and the fourth analog signal isgenerated based on a fourth sampling clock having a 25% duty cycle, thefourth sampling clock having the same frequency and having a phase shiftof 270° as compared to the first sampling clock.

Aspect 20. The method of claim 17, wherein: the first analog signal isgenerated based on a first sampling clock; the second analog signal isgenerated based on a second sampling clock having a 25% duty cycle, thesecond sampling clock having the same frequency and having a phase shiftof 180° as compared to the first sampling clock; the third analog signalis generated based on a third sampling clock having a 25% duty cycle,the third sampling clock having the same frequency and having a phaseshift of 90° as compared to the first sampling clock; and the fourthanalog signal is generated based on a fourth sampling clock having a 25%duty cycle, the fourth sampling clock having the same frequency andhaving a phase shift of 270° as compared to the first sampling clock.

Aspect 21. The method of claim 14, wherein: the first analog signal isgenerated based on a first sampling clock; the second analog signal isgenerated based on a second sampling clock having a 66% duty cycle, thesecond sampling clock having the same frequency and having a phase shiftof 120° as compared to the first sampling clock; and the third analogsignal is generated based on a third sampling clock having a 33% dutycycle, the third sampling clock having the same frequency and having aphase shift of 240° as compared to the first sampling clock.

Aspect 22. The method of claim 13, further comprising: generating, via afirst filter circuit, a first filtered version of the digital inputsignal, wherein the first analog signal is generated based on the firstfiltered version of the digital input signal; and generating, via asecond filter circuit, a second filtered version of the digital inputsignal, wherein the second analog signal is generated based on thesecond filtered version of the digital input signal.

Aspect 23. The method of claim 13, wherein the second analog signal hasa magnitude that is equal to a difference between the first analogsignal and a value representing the digital input signal.

Aspect 24. The method of claim 13, wherein the DAC comprises azero-order hold DAC.

Aspect 25. An apparatus for digital-to-analog conversion, comprising: adigital-to-analog converter (DAC) configured to generate a first analogsignal by performing digital-to-analog conversion based on a digitalinput signal; a first return-to-zero (RZ) DAC configured to generate asecond analog signal by performing digital-to-analog conversion based onthe digital input signal; and a combiner configured to combine the firstanalog signal and the second analog signal to generate a combined analogsignal.

Aspect 26. The apparatus of claim 25, further comprising a second RZ DACconfigured to generate a third analog signal based on the digital inputsignal, wherein the combiner is configured to combine the first analogsignal, the second analog signal, and the third analog signal.

Aspect 27. The apparatus of claim 26, wherein: the DAC is configured togenerate the first analog signal based on a first sampling clock; thefirst RZ DAC is configured to generate the second analog signal based ona second sampling clock, the second sampling clock having the samefrequency as the first sampling clock; and the second RZ DAC isconfigured to generate the third analog signal based on a third samplingclock, the third sampling clock having a frequency that is twice thefrequency of the first sampling clock.

Aspect 28. The apparatus of claim 27, wherein the second sampling clockis phase shifted from the first sampling clock by 180°.

Aspect 29. The apparatus of claim 26, further comprising a third RZ DACconfigured to generate a fourth analog signal based on the digital inputsignal, wherein the combiner is configured to combine the first analogsignal, the second analog signal, the third analog signal, and thefourth analog signal.

Aspect 30. The apparatus of claim 29, wherein: the DAC is configured togenerate the first analog signal based on a first sampling clock; thefirst RZ DAC is configured to generate the second analog signal based ona second sampling clock, the second sampling clock having the samefrequency and having a phase shift of 180° as compared to the firstsampling clock; the second RZ DAC is configured to generate the thirdanalog signal based on a third sampling clock having a 25% duty cycle,the third sampling clock having the same frequency and having a phaseshift of 90° as compared to the first sampling clock; and the third RZDAC is configured to generate the fourth analog signal based on a fourthsampling clock having a 25% duty cycle, the fourth sampling clock havingthe same frequency and having a phase shift of 270° as compared to thefirst sampling clock.

The various operations of methods described above may be performed byany suitable means capable of performing the corresponding functions.The means may include various hardware component(s) and/or module(s),including, but not limited to one or more circuits. Generally, wherethere are operations illustrated in figures, those operations may havecorresponding counterpart means-plus-function components with similarnumbering. Means for generating may include a digital-to-analogconverter (DAC), such as the DAC 502 or DACs 504. Means for combiningmay include a combiner, such as the combiner 510.

As used herein, the term “determining” encompasses a wide variety ofactions. For example, “determining” may include calculating, computing,processing, deriving, investigating, looking up (e.g., looking up in atable, a database, or another data structure), ascertaining, and thelike. Also, “determining” may include receiving (e.g., receivinginformation), accessing (e.g., accessing data in a memory), and thelike. Also, “determining” may include resolving, selecting, choosing,establishing, and the like.

As used herein, a phrase referring to “at least one of” a list of itemsrefers to any combination of those items, including single members. Asan example, “at least one of: a, b, or c” is intended to cover: a, b, c,a-b, a-c, b-c, and a-b-c, as well as any combination with multiples ofthe same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b,b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c).

The various illustrative logical blocks, modules, and circuits describedin connection with the present disclosure may be implemented orperformed with discrete hardware components designed to perform thefunctions described herein.

The methods disclosed herein comprise one or more steps or actions forachieving the described method. The method steps and/or actions may beinterchanged with one another without departing from the scope of theclaims. In other words, unless a specific order of steps or actions isspecified, the order and/or use of specific steps and/or actions may bemodified without departing from the scope of the claims.

It is to be understood that the claims are not limited to the preciseconfiguration and components illustrated above. Various modifications,changes and variations may be made in the arrangement, operation anddetails of the methods and apparatus described above without departingfrom the scope of the claims.

What is claimed is:
 1. A device for digital-to-analog conversion,comprising: a digital-to-analog converter (DAC) having an input coupledto an input node of the device, wherein the DAC is not a return-to-zero(RZ) DAC; a first RZ DAC having an input coupled to the input node ofthe device; and a combiner, wherein an output of the DAC is coupled to afirst input of the combiner and wherein an output of the first RZ DAC iscoupled to a second input of the combiner.
 2. The device of claim 1,further comprising a second RZ DAC having an input coupled to the inputnode of the device, wherein an output of the second RZ DAC is coupled toa third input of the combiner.
 3. The device of claim 2, wherein: theDAC is configured to perform digital-to-analog conversion of an inputsignal at the input node based on a first sampling clock; the first RZDAC is configured to perform digital-to-analog conversion of the inputsignal based on a second sampling clock, the second sampling clockhaving the same frequency as the first sampling clock; and the second RZDAC is configured to perform digital-to-analog conversion of the inputsignal based on a third sampling clock, the third sampling clock havinga frequency that is twice the frequency of the first sampling clock. 4.The device of claim 3, wherein the second sampling clock is phaseshifted from the first sampling clock by 180°.
 5. The device of claim 2,further comprising a third RZ DAC having an input coupled to the inputnode of the device, wherein an output of the third RZ DAC is coupled toa fourth input of the combiner.
 6. The device of claim 5, wherein: theDAC is configured to perform digital-to-analog conversion of an inputsignal at the input node based on a first sampling clock; the first RZDAC is configured to perform digital-to-analog conversion of the inputsignal based on a second sampling clock, the second sampling clockhaving the same frequency and having a phase shift of 180° as comparedto the first sampling clock; the second RZ DAC is configured to performdigital-to-analog conversion of the input signal based on a thirdsampling clock having a 25% duty cycle, the third sampling clock havingthe same frequency and having a phase shift of 90° as compared to thefirst sampling clock; and the third RZ DAC is configured to performdigital-to-analog conversion of the input signal based on a fourthsampling clock having a 25% duty cycle, the fourth sampling clock havingthe same frequency and having a phase shift of 270° as compared to thefirst sampling clock.
 7. The device of claim 5, wherein: the DAC isconfigured to perform digital-to-analog conversion of an input signal atthe input node based on a first sampling clock; the first RZ DAC isconfigured to perform digital-to-analog conversion of the input signalbased on a second sampling clock, the second sampling clock having thesame frequency and having a phase shift of 180° as compared to the firstsampling clock; the second RZ DAC is configured to performdigital-to-analog conversion of the input signal based on a thirdsampling clock having a 75% duty cycle, the third sampling clock havingthe same frequency and having a phase shift of 90° as compared to thefirst sampling clock; and the third RZ DAC is configured to performdigital-to-analog conversion of the input signal based on a fourthsampling clock having a 25% duty cycle, the fourth sampling clock havingthe same frequency and having a phase shift of 270° as compared to thefirst sampling clock.
 8. The device of claim 5, wherein: the DAC isconfigured to perform digital-to-analog conversion of an input signal atthe input node based on a first sampling clock; the first RZ DAC isconfigured to perform digital-to-analog conversion of the input signalbased on a second sampling clock having a 25% duty cycle, the secondsampling clock having the same frequency and having a phase shift of180° as compared to the first sampling clock; the second RZ DAC isconfigured to perform digital-to-analog conversion of the input signalbased on a third sampling clock having a 25% duty cycle, the thirdsampling clock having the same frequency and having a phase shift of 90°as compared to the first sampling clock; and the third RZ DAC isconfigured to perform digital-to-analog conversion of the input signalbased on a fourth sampling clock having a 25% duty cycle, the fourthsampling clock having the same frequency and having a phase shift of270° as compared to the first sampling clock.
 9. The device of claim 2,wherein: the DAC is configured to perform digital-to-analog conversionof an input signal at the input node based on a first sampling clock;the first RZ DAC is configured to perform digital-to-analog conversionof the input signal based on a second sampling clock having a 66% dutycycle, the second sampling clock having the same frequency and having aphase shift of 120° as compared to the first sampling clock; and thesecond RZ DAC is configured to perform digital-to-analog conversion ofthe input signal based on a third sampling clock having a 33% dutycycle, the third sampling clock having the same frequency and having aphase shift of 240° as compared to the first sampling clock.
 10. Thedevice of claim 1, further comprising: a first filter circuit coupledbetween the input node of the device and the input of the DAC; and asecond filter circuit coupled between the input node of the device andthe input of the DAC, wherein the second filter circuit has a differenttransfer function than the first filter circuit.
 11. The device of claim1, wherein: the DAC is configured to generate a first analog signalbased on a digital input signal; and the first RZ DAC is configured togenerate a second analog signal, the second analog signal having amagnitude that is equal to a difference between the first analog signaland a value representing the digital input signal.
 12. The device ofclaim 1, wherein the first DAC comprises a zero-order hold DAC.
 13. Amethod for digital-to-analog conversion, comprising: generating, via adigital-to-analog converter (DAC), a first analog signal by performingdigital-to-analog conversion based on a digital input signal, whereinthe DAC is not a return-to-zero (RZ) DAC; generating, via a first RZDAC, a second analog signal by performing digital-to-analog conversionbased on the digital input signal; and combining the first analog signaland the second analog signal to generate a combined analog signal. 14.The method of claim 13, further comprising generating, via a second RZDAC, a third analog signal based on the digital input signal, whereinthe combining includes combining the first analog signal, the secondanalog signal, and the third analog signal.
 15. The method of claim 14,wherein: the first analog signal is generated based on a first samplingclock; the second analog signal is generated based on a second samplingclock, the second sampling clock having the same frequency as the firstsampling clock; and the third analog signal is generated based on athird sampling clock, the third sampling clock having a frequency thatis twice the frequency of the first sampling clock.
 16. The method ofclaim 15, wherein the second sampling clock is phase shifted from thefirst sampling clock by 180°.
 17. The method of claim 14, furthercomprising: generating, via a third RZ DAC, a fourth analog signal basedon the digital input signal, wherein the combining includes combiningthe first analog signal, the second analog signal, the third analogsignal, and the fourth analog signal.
 18. The method of claim 17,wherein: the first analog signal is generated based on a first samplingclock; the second analog signal is generated based on a second samplingclock, the second sampling clock having the same frequency and having aphase shift of 180° as compared to the first sampling clock; the thirdanalog signal is generated based on a third sampling clock having a 25%duty cycle, the third sampling clock having the same frequency andhaving a phase shift of 90° as compared to the first sampling clock; andthe fourth analog signal is generated based on a fourth sampling clockhaving a 25% duty cycle, the fourth sampling clock having the samefrequency and having a phase shift of 270° as compared to the firstsampling clock.
 19. The method of claim 17, wherein: the first analogsignal is generated based on a first sampling clock; the second analogsignal is generated based on a second sampling clock, the secondsampling clock having the same frequency and having a phase shift of180° as compared to the first sampling clock; the third analog signal isgenerated based on a third sampling clock having a 75% duty cycle, thethird sampling clock having the same frequency and having a phase shiftof 90° as compared to the first sampling clock; and the fourth analogsignal is generated based on a fourth sampling clock having a 25% dutycycle, the fourth sampling clock having the same frequency and having aphase shift of 270° as compared to the first sampling clock.
 20. Themethod of claim 17, wherein: the first analog signal is generated basedon a first sampling clock; the second analog signal is generated basedon a second sampling clock having a 25% duty cycle, the second samplingclock having the same frequency and having a phase shift of 180° ascompared to the first sampling clock; the third analog signal isgenerated based on a third sampling clock having a 25% duty cycle, thethird sampling clock having the same frequency and having a phase shiftof 90° as compared to the first sampling clock; and the fourth analogsignal is generated based on a fourth sampling clock having a 25% dutycycle, the fourth sampling clock having the same frequency and having aphase shift of 270° as compared to the first sampling clock.
 21. Themethod of claim 14, wherein: the first analog signal is generated basedon a first sampling clock; the second analog signal is generated basedon a second sampling clock having a 66% duty cycle, the second samplingclock having the same frequency and having a phase shift of 120° ascompared to the first sampling clock; and the third analog signal isgenerated based on a third sampling clock having a 33% duty cycle, thethird sampling clock having the same frequency and having a phase shiftof 240° as compared to the first sampling clock.
 22. The method of claim13, further comprising: generating, via a first filter circuit, a firstfiltered version of the digital input signal, wherein the first analogsignal is generated based on the first filtered version of the digitalinput signal; and generating, via a second filter circuit, a secondfiltered version of the digital input signal, wherein the second analogsignal is generated based on the second filtered version of the digitalinput signal.
 23. The method of claim 13, wherein the second analogsignal has a magnitude that is equal to a difference between the firstanalog signal and a value representing the digital input signal.
 24. Themethod of claim 13, wherein the DAC comprises a zero-order hold DAC. 25.An apparatus for digital-to-analog conversion, comprising: adigital-to-analog converter (DAC) configured to generate a first analogsignal by performing digital-to-analog conversion based on a digitalinput signal; a first return-to-zero (RZ) DAC configured to generate asecond analog signal by performing digital-to-analog conversion based onthe digital input signal, wherein the DAC is a different type of DACthan the first RZ DAC; and a combiner configured to combine the firstanalog signal and the second analog signal to generate a combined analogsignal.
 26. The apparatus of claim 25, further comprising a second RZDAC configured to generate a third analog signal based on the digitalinput signal, wherein the combiner is configured to combine the firstanalog signal, the second analog signal, and the third analog signal.27. The apparatus of claim 26, wherein: the DAC is configured togenerate the first analog signal based on a first sampling clock; thefirst RZ DAC is configured to generate the second analog signal based ona second sampling clock, the second sampling clock having the samefrequency as the first sampling clock; and the second RZ DAC isconfigured to generate the third analog signal based on a third samplingclock, the third sampling clock having a frequency that is twice thefrequency of the first sampling clock.
 28. The apparatus of claim 27,wherein the second sampling clock is phase shifted from the firstsampling clock by 180°.
 29. The apparatus of claim 26, furthercomprising a third RZ DAC configured to generate a fourth analog signalbased on the digital input signal, wherein the combiner is configured tocombine the first analog signal, the second analog signal, the thirdanalog signal, and the fourth analog signal.
 30. The apparatus of claim29, wherein: the DAC is configured to generate the first analog signalbased on a first sampling clock; the first RZ DAC is configured togenerate the second analog signal based on a second sampling clock, thesecond sampling clock having the same frequency and having a phase shiftof 180° as compared to the first sampling clock; the second RZ DAC isconfigured to generate the third analog signal based on a third samplingclock having a 25% duty cycle, the third sampling clock having the samefrequency and having a phase shift of 90° as compared to the firstsampling clock; and the third RZ DAC is configured to generate thefourth analog signal based on a fourth sampling clock having a 25% dutycycle, the fourth sampling clock having the same frequency and having aphase shift of 270° as compared to the first sampling clock.